Photolithography is one of the most frequently employed semiconductor wafer processing techniques used to manufacture integrated circuits (IC's). Photolithography comprises a process for forming a pattern (i.e., via photographic transfer) of complex circuit structures onto a semiconductor wafer surface for patterning. These patterns are defined on the wafer in a succession of exposure and processing steps to form a number of superimposed layers. Manufacturing processes for IC devices depend upon extremely accurate reproduction of these patterns onto the wafer surface in order to produce uniform features. A certain accuracy and precision in forming features by photolithography is necessary for proper performance matching of certain features at a local and at a global (i.e., chip) level. The importance of the accuracy and precision increases with decreasing feature size, to which the industry is trending.
During each photolithographic step, unintended deviations are commonly introduced that distort the photomask image being transferred onto the chip areas of a wafer surface. These deviations depend on the characteristics of a pattern being transferred, the topographic elevation of the chip areas, and a variety of other processing parameters. Processing deviations adversely affect the performance of a semiconductor device. In particular, when a layer of photoresist is deposited on a wafer surface, such as by spin coating, the uniformity of the photoresist layer thickness is known to be distorted by the density and arrangement of the features that contribute to the topographic elevation of the chip areas. For instance, where the local features in one region are relatively dense and the features in an adjacent region are relatively less dense, the top surface of the layer of photoresist frequently slopes downward from the former to the latter. Further, the photoresist thickness may vary irregularly around various densities and arrangements of features. Thus, a patterning of a number of similar features, such as resistors, in a region of sloping or irregular photoresist thickness may result in unequal dimensions and performance of such features. For example, due to the effects of different densities, shapes and/or heights of “upstream” features (i.e., toward the source of photoresist), photoresist thickness will vary for each of the two purportedly matched resistors. Then, one resistor may have an overall wider conductor linewidth while the other purportedly matched resistor has a narrower overall linewidth. This will result in unequal performance of the two purportedly matched resistors (i.e., local mismatching of devices).
In view of this example and more generally, the photolithographic process of forming patterns and features on a wafer is sensitive to the wafer topographic elevation. Existing differences in topographic elevation, prior to deposition of photoresist, can result in a variation in photoresist thickness over a relatively long (but still local) distance. Such a photoresist thickness change induces a linewidth or other change from the specification for a given pattern. This change from specification results in performance differences from specification, and such differences are manifested when multiple devices are being formed in an area that includes the photoresist thickness change. This results in local mismatching of devices. The following publication, which is incorporated by reference herein, describes a number of sources of mismatches in addition to such topography-related phenomenon, “Design of Matching Test Structures,” H. P. Tuinhout, Proc. IEEE 1994 Int'l. Conference on Microelectronic Test Structures, Vol. 7, page 21-23, March 1994.
Those skilled in the art have addressed variation in photoresist thickness due to flow over irregular chip topography. A customary approach to reduce or eliminate the impact of gradual photoresist thickness change, and other factors, over a relatively small spatial dimension is to arrange the devices in a common centroid layout, particularly with interdigitated fingers with dummies. A centroid is defined generally as the center of mass. A common centroid arrangement of two devices, for example, occurs when the features of the respective devices are arranged such that both devices have the same center of mass. Often in chip design an array of multiple similar segments (i.e., fingers) comprise one device, and this is arranged in a particular pattern with a second similarly comprised device in a pattern by which both devices have the same centroid (i.e., a common centroid).
A common centroid layout may be one-dimensional or two-dimensional. A one-dimensional common centroid layout provides identical matched devices arranged to form a symmetrical pattern of their respective segments such that the so-arranged devices share a common axis of symmetry. For instance, FIG. 1a depicts matched devices A and B arranged with segments ABBA, where there is a common axis of symmetry 10 between the two B segments. These devices also share a central, common centroid, designated by the “X” in the center of the common axis of symmetry 10. Typically, since the two A segments are on the exterior, leveling segments are added in order for each segment to be next to a similar arrangement of geometries (thereby addressing iso-nested bias). Another one-dimensional common centroid pattern is depicted as ABABAB. Here, one A and one B segment comprise the end segments. A two-dimensional common centroid layout derives both of its axes from its interdigitating pattern. Examples are depicted in FIGS. 1b and 1c. 
However, devices in common centroid layouts are nonetheless subject to linewidth variation caused by photoresist thickness variations. Such thickness variations may be caused by variation due to an uneven flow over and other effects from local features that come to lie underneath the photoresist layer (i.e., “underlying features”). Further, problems with global matching, that is, the performance equivalence of devices (or arrays of devices) spaced a distance from one another on an integrated circuit, may result when there is different local topographic elevation near, for instance, two relatively distant devices (or arrays of devices) that are designed to have matched performance. The importance of the symmetry and precision of matched devices, to provide acceptable performance, is recognized for many device types, such as, but not limited to, resistors, capacitors, and transistors.
As to the presence of multiple relatively nearby features that may affect photoresist thickness in an area later used for matched devices, present designs result in a random and complex effect of such nearby underlying features. This is better understood in consideration of how photoresist is applied. Typically photoresist is applied over a wafer that is spinning, such as between 1,000 and 8,000 revolutions per minute. Based on the sum effects of the particular composition of the photoresist and viscosity, the spin speed, and the temperature, and other factors, the thickness of the photoresist layer across the wafer surface tends to a particular fixed value. Across a relatively uniform area of the wafer, such as a large block of thick polysilicon, where there are no nearby raised features between the area and the point of application of the photoresist, the photoresist thickness tends toward this fixed value. This may be considered to be the “flat-wafer equilibrium thickness.”
It is noted that the thicknesses typical of photoresist layers applied to IC wafers are relatively thin, in an order of magnitude of about 1.0 micron. It is appreciated that physical/chemical effects, such as surface tension, charge effects and interactions, and general rheological properties at this thinness of photoresist may cause the photoresist thickness to behave in ways not expected based on the behavior of relatively thicker layers. In view of this particular environment, the present invention provides advances in the art.
More particularly, the leveling guard ring technology as described and claimed herein addresses a need for improvements in topographic elevation and device layout to better ensure improved local and/or global matching. This becomes increasingly important as size requirements for features becomes increasingly smaller, and given the variable design arrangements in which one or more relatively nearby underlying features may crucially distort a photoresist layer thickness.